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參數(shù)資料
| 型號(hào)： | S2068 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual GigaBit Ethernet Transceiver(雙千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 雙千兆以太網(wǎng)收發(fā)器（雙千兆位以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 5/24頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | S2068 |
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5
S2068
DUAL GIGABIT ETHERNET TRANSCEIVER
October 13, 2000 / Revision D
TRANSMITTER DESCRIPTION
The transmitter section of the S2068 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Transmitter
functionalities shown schematically in Figure 3. Two
channels are provided with a variety of options re-
garding input clocking and loopback. The transmit-
ters operate at 1.250 GHz, 10 or 20 times the
reference clock frequency.
Data Input
The S2068 has been designed to simplify the paral-
lel interface data transfer and provides flexibility in
the clocking of parallel data. Prior implementations
of this function have either forced the user to syn-
chronize transmit data to the reference clock or to
provide the output clock as a reference to the PLL,
resulting in increased jitter at the serial interface.
The S2068 incorporates a unique FIFO structure
which enables the user to provide a “clean” refer-
ence source for the PLL and to accept a separate
external clock which is used exclusively to reliably
clock data into the device.
The S2068 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock. See Table 1.
Data to be input to the S2068 should be coded to
ensure transition density and DC balance. Data is
input to each channel of the S2068 as a 10 bit wide
word. An input FIFO and a clock input,
TBCx, are
provided for each channel of the S2068. This device
can operate in two different modes. The S2068 can
be configured to use either the TBCx (TBC MODE)
input or the REFCLK input (REFCLK MODE). Table
2 provides a summary of the input modes for the
S2068.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 125 Mbit/sec 10 bit interface.
The TBC signal is used to clock the data into an
internal holding register and the S2068 synchronizes
its internal data flow to ensure stable operation.
REFCLK, not TBCx, is used as the reference for the
transmit PLL. This ensures minimum jitter on the
high speed serial data stream.
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Table 1. Operating Rates
REFCLK
S2068
125 MHz or 62.5 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
Figure 5. DIN Clocking with TBC
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
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Table 2. Input Modes
Note: SDR = Serial Data Rate.
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相關(guān)代理商/技術(shù)參數(shù) |
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