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參數(shù)資料
| 型號： | S2053 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據(jù)傳送的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 125K |
| 代理商： | S2053 |
3
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2053
REFCLKP/N
TREFCLK
(Input)
RBC0
(Output)
COM_DET
(Output)
PARALLEL
DATA BUS
(Input)
PARALLEL
DATA BUS
(Output)
SERIAL DATA
K28.5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
K28.5
K28.5
K28.5
K28.5
K28.5
RBC1
(Output)
INPUT TIMING
OUTPUT TIMING
Figure 4. Functional Waveform (1250 and 1062.5 Mbit/sec)
Table 1. Data Mapping to 8b/10b
Alphabetic Representation
TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2053 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The chip is fully compatible with the ANSI
X3T11 Fibre Channel standard, and supports the Fi-
bre Channel Gigabit Ethernet standard’s data rates of
1250 and 1062 Mbit/sec. (See Figure 3.)
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmitter
on the positive going edge of the reference clock.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10x of the reference clock
inputfrequency. D0 is transmitted first as described in
annex N and Tables 22 and 23 of FC-PH. Table 1
shows the mapping of the parallel data to the 8B/10B
codes.
Reference Clock Input (Transmit Byte Clock)
The reference clock input must be supplied with a
clock source with 100 PPM tolerance to assure that
the transmitted data meets the Fibre Channel frequency
limits. The internal serial clock is frequency locked to the
reference clock (125.00 and 106.25 MHz).
RECEIVER FUNCTIONAL DESCRIPTION
The S2053 receiver is designed to implement the ANSI
X3T11 Fibre Channel specification and the IEEE 802.3z
Gigabit Ethernet receiver functions. A block diagram
showing the basic chip function is provided in Figure 3.
Whenever a signal is present, the S2053 attempts to
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device’s parallel data outputs.
The S2053 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream is
the result of the serialization of 8B/10B encoded data by
an FC compatible transmitter. Clock recovery is performed
on-chip, with the output data presented to the Fibre
Channel transmission layer as 10-bit parallel data.
Data Byte
9
8
7
6
5
4
3
2
1
0
TX[0:9] or
RX[0:9]
8b/10b alphabetic
representation
j
h
g
f
i
e
d
c
b
a
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2054 | Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發(fā)送串行I/O的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| S2055A | SILICON DIFFUSED POWER TRANSISTOR |
| S2057 | Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網(wǎng)的端口旁路電路) |
| S2058 | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器) |
| S2060 | GIGABIT ETHERNET TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2054AG4 | 制造商:TYAN 功能描述:M-ATX SOCKET-370 INTEL 810 - Bulk |
| S2055 | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
| S2055A | 制造商:SAVANTIC 制造商全稱:Savantic, Inc. 功能描述:Silicon NPN Power Transistors |
| S2055AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR |
| S2055F | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
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