- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374646 > S2042 (Applied Micro Circuits Corp.) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS PDF資料下載
參數(shù)資料
| 型號： | S2042 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS |
| 中文描述： | 高性能串行接口電路 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 241K |
| 代理商： | S2042 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
3
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2043
Reference Clock Input
The reference clock input (REFCLK) must be sup-
plied with a single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the
transmitted data meets the Fibre Channel frequency
limits. The internal serial clock is frequency locked to
the reference clock. The word rate clock (TCLK, TCLKN)
output frequency is determined by the selected oper-
ating speed and word width. Refer to Table 1 for
TCLK/TCLKN clock frequencies.
Table 1. Transmitter Operating Modes
Data Rate
(Mbits/sec)
1062.5
1062.5
RATESEL
0
0
REFSEL
1
0
DWS
1
0
Word
Width
(Bits)
10
20
Reference
Clock
Frequency
(MHz)
106.25
53.125
531.25
531.25
265.625
1
1
Open
10
20
10
1
0
1
TCLK/TCLKN
Frequency
(MHz)
53.125
53.125
53.125
26.5625
26.5625
53.125
26.5625
26.5625
1
0
1
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 times the REFCLK
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D10 is transmitted first in 10-bit mode. D0 is trans-
mitted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
10-Bit/20-Bit Mode
The S2042 operates with either 10-bit or 20-bit par-
allel data inputs. Word width is selectable via the
DWS pin. In 10-bit mode, D10–D19 are used and
D0–D9 are ignored.
First Data Byte
Second Data Byte
19
18
17
16
15
14
13
12
11
10
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
TX[00:19] or
RX[00:19]
8b/10b alphabetic
representation
j
h
g
f
i
e
d
c
b
a
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Table 2. Data Mapping to 8b/10b Alphabetic Representation
Figure 4. S2043 Functional Block Diagram
PLL CLOCK
RECOVERY
2:1
D
20
D
BITCLK
Q
SYNC
DETECT
LOGIC
CONTROL
LOGIC
RX
RY
REFCLK
REFSEL
RATESEL
LOCK_REF
RLX
RLY
LPEN
DWS
SYNCEN
LOCKDETN
D(0..19)
RCLK
SYNC
RCLKN
SHIFT
REGISTER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2043 | HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS |
| S2052 | Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據(jù)傳送的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| S2053 | Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據(jù)傳送的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| S2054 | Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發(fā)送串行I/O的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| S2055A | SILICON DIFFUSED POWER TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S20420 | 制造商:Microsemi Corporation 功能描述:STD RECOVERY RECTFR 200V 12A 2PIN DO-4 - Bulk 制造商:Microsemi Corporation 功能描述:Diode Switching 200V 12A 2-Pin DO-4 |
| S204201N1124 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:SILICON POWER RECTIFIER |
| S204201N1124A | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:SILICON POWER RECTIFIER |
| S204201N1125 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:SILICON POWER RECTIFIER |
| S204201N1125A | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:SILICON POWER RECTIFIER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。