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參數(shù)資料
| 型號(hào)： | S2002 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器) |
| 中文描述： | 雙串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器） |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 311K |
| 代理商： | S2002 |
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9
S2002
DUAL SERIAL BACKPLANE DEVICE
October 9, 2000 / Revision B
Table 3. K Character Generation (DNx = 1 KGENx =1 SYNC = 0)
K
a
r
r
e
a
h
C
]
N
I
D
N
E
G
K
+
D
R
t
n
e
r
u
C
-
D
R
t
n
e
r
u
C
s
n
e
m
m
o
C
j
g
f
i
d
c
b
a
j
g
f
i
d
c
b
a
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
7
2
7
2
7
2
7
3
K
K
K
K
K
K
K
K
K
K
K
K
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
r
a
h
C
c
n
y
S
Table 4. Data to 8B/10B Alphabetic Representation
e
B
a
D
]
U
O
D
r
]
N
I
D
0
1
2
3
4
5
6
7
8
9
B
0
1
B
8
n
o
e
s
e
e
R
c
m
u
n
a
h
p
a
b
c
d
e
i
f
g
h
j
Table 5. Operating Rates
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 5.
Serial Data Outputs
The S2002 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. The transmit FIFO
is also reset when the special synchronization pat-
tern (SYNC=1, DN=1) is generated. TCLKO will op-
erate normally regardless of the state of RESET.
E
T
A
R
L
E
S
K
L
C
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
t
u
p
t
u
O
l
e
S
e
R
O
n
K
e
L
u
C
q
T
e
r
y
c
F
0
0
0
1
R
D
S
z
H
G
3
–
8
9
0
1
R
D
S
0
1
0
2
R
D
S
z
H
G
3
–
8
9
0
1
R
D
S
1
0
0
1
R
D
S
z
H
G
5
6
–
9
4
0
1
R
D
S
1
1
0
2
R
D
S
z
H
G
5
6
–
9
4
0
1
R
D
S
Note: SDR = Serial Data Rate
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