參數(shù)資料
型號: S1C63458F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP144
封裝: QFP-144
文件頁數(shù): 67/144頁
文件大?。?/td> 1156K
代理商: S1C63458F0A0100
S1C63458 TECHNICAL MANUAL
EPSON
19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF48H
IOC23
IOC22
IOC21
IOC20
R/W
IOC23
IOC22
IOC21
IOC20
0
Output
Input
P23 I/O control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O control register
P20 I/O control register
FF49H
PUL23
PUL22
PUL21
PUL20
R/W
PUL23
PUL22
PUL21
PUL20
1
On
Off
P23 pull-up control register (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 pull-up control register (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 pull-up control register
P20 pull-up control register
FF4AH
P23
P22
P21
P20
R/W
P23
P22
P21
P20
2
High
Low
P23 I/O port data (EXLCDC=0)
functions as a general-purpose register when FR output is selected
P22 I/O port data (EXLCDC=0)
functions as a general-purpose register when CL output is selected
P21 I/O port data
P20 I/O port data
FF60H
LDUTY1 LDUTY0 VCCHG LPWR
R/W
LDUTY1
LDUTY0
VCCHG
LPWR
0
VC2
On
VC1
Off
LCD drive duty
switch
LCD regulated voltage switch
LCD power On/Off
0
1/17
1
1/16
2, 3
1/8
[LDUTY1, 0]
Duty
0
Light
15
Dark
[LC3–0]
Contrast
FF61H
EXLCDC ALOFF
ALON
LPAGE
R/W
EXLCDC
ALOFF
ALON
LPAGE
0
1
0
Enable
All Off
All On
F100-F177
Disable
Normal
F000-F077
Expanded LCD driver signal control
LCD all OFF control
LCD all ON control
Display memory area selection (when 1/8 duty is selected)
functions as a general-purpose register when 1/16, 1/17 duty is selected
FF62H
LC3
LC2
LC1
LC0
R/W
LC3
LC2
LC1
LC0
2
LCD contrast adjustment
0
4096.0
1
3276.8
2
2730.7
3
2340.6
[BZFQ2, 1, 0]
Frequency (Hz)
4
2048.0
5
1638.4
6
1365.3
7
1170.3
[BZFQ2, 1, 0]
Frequency (Hz)
FF6EH
0
BZFQ2
BZFQ1
BZFQ0
R
R/W
0 3
BZFQ2
BZFQ1
BZFQ0
2
0
Unused
Buzzer
frequency
selection
FF6FH
0
BDTY2
BDTY1
BDTY0
R
R/W
0 3
BDTY2
BDTY1
BDTY0
2
0
Unused
Buzzer signal duty ratio selection
(refer to main manual)
FF6CH
ENRTM ENRST
ENON
BZE
R/W
W
R/W
ENRTM
ENRST3
ENON
BZE
0
Reset
0
1 sec
Reset
On
Enable
0.5 sec
Invalid
Off
Disable
Envelope releasing time
Envelope reset (writing)
Envelope On/Off
Buzzer output enable
FF6DH
0
BZSTP BZSHT SHTPW
RW
R/W
0 3
BZSTP3
BZSHT
SHTPW
2
0
Stop
Trigger
Busy
125 msec
Invalid
Ready
31.25 msec
Unused
1-shot buzzer stop (writing)
1-shot buzzer trigger (writing)
1-shot buzzer status (reading)
1-shot buzzer pulse width setting
0
Slave
2
OSC1/2
1
PT
3
OSC1
[SCS1, 0]
Clock
[SCS1, 0]
Clock
FF71H
SDP
SCPS
SCS1
SCS0
R/W
SDP
SCPS
SCS1
SCS0
0
MSB first LSB first Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
FF70H
00
SCTRG
ESIF
R
R/W
0 3
SCTRG
ESIF
2
0
Trigger
Run
SIF
Invalid
Stop
I/O
Unused
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
Table 4.1.1 (c) I/O memory map (FF48H–FF71H)
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