II-102
EPSON
S1C62440/624A0/624C0/62480 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Interrupt)
(1) The interrupt factor flag is set when the interrupt condi-
tions are established, regardless of the setting of the
interrupt mask register. Note, however, that the input
interrupt factor flags (IK0 and IK1) will be eliminated.
(2) Be sure that the interrupt factor flag reading is done with
the interrupt in the DISABLE state (DI). Reading the
interrupt factor flag while in the ENABLE state (EI) may
cause malfunction.
(3) Be sure that writing to the interrupt mask register is
done with the interrupt in the DISABLE state (DI). Writ-
ing to the interrupt mask register while in the ENABLE
state (EI) may cause malfunction.
(4) When multiple interrupts simultaneously occur, the high
priority vector address is set to the program counter.
(5) If an interrupt occurs while the CPU is processing some
other interrupt request of which the priority is lower than
the new one but the CPU has not fetched the interrupt
vector, the CPU may shift to a vector address (one of
among 102H, 104H, 106H, 10AH and 10EH) that is
different from the new interrupt.
Therefore, make sure the interrupt factor flag has been
set immediately after the branch instruction stored in the
vector address is executed and quit the interrupt process-
ing if it has not been set.
Furthermore, place a branch instruction for executing the
interrupt processing routine in the vector address 10EH
because the CPU may shift to that address. By setting the
start address of the programmable timer interrupt pro-
cessing routine as the branch destination, the priority
level by hardware can be maintained.
Programming notes
Program example 1:
To quit the interrupt processing if the interrupt factor flag
has not been set
0100H
PSET
NIT
0101H
JP
INIT
0102H
PSET
TM_INT
0103H
JP
TM_INT
0104H
PSET
SW_INT
0105H
JP
SW_INT
0106H
PSET
K0X_INT