參數(shù)資料
型號: S1C60N01F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48
封裝: PLASTIC, QFP12-48
文件頁數(shù): 70/153頁
文件大?。?/td> 901K
代理商: S1C60N01F
S1C60N01 TECHNICAL HARDWARE
EPSON
I-11
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAM
CPU
The S1C60N01 Series employs the S1C6200B core CPU, so
that register configuration, instructions, and so forth are
virtually identical to those in other processors in the family
using the S1C6200B. Refer to the "S1C6200/6200A Core
CPU Manual" for details of the S1C6200B.
Note the following points with regard to the S1C60N01
Series:
(1) The SLEEP operation is not provided, so the SLP instruc-
tion cannot be used.
(2) Because the ROM capacity is 1,024 words, 12 bits per
word, bank bits are unnecessary, and PCB and NBP are
not used.
(3) The RAM page is set to 0 only, so the page part (XP, YP)
of the index register that specifies addresses is invalid.
PUSH
XP
PUSH
YP
POP
XP
POP
YP
LD
XP,r
LD
YP,r
LD
r,XP
LD
r,YP
CHAPTER 3
3.1
相關(guān)PDF資料
PDF描述
S1C60N02D 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC52
S1C60L02 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60
S1C60N04D 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48
S1C60N08D 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC96
S1C60N08F0A0100 MICROCONTROLLER, PQFP100
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