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參數(shù)資料
| 型號： | S1C60L02F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 |
| 封裝： | PLASTIC, QFP6-60 |
| 文件頁數(shù)： | 63/102頁 |
| 文件大?。?/td> | 674K |
| 代理商： | S1C60L02F |
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S1C60N02 TECHNICAL MANUAL
EPSON
55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Input clock selection (0FEH D0)
Select the input clock of the up/down counter TC0–TC15.
When "1" is written:
65 kHz
When "0" is written:
32 kHz
Reading:
Valid
Select the output clock of the multiplying circuit for the
counting operation of the up/down counter TC0–TC15.
When "1" is written in the ADCLK, 65 kHz, a multitude of
the OSC1 clock is selected. When "0" is written, the OSC1
clock is selected at 32 kHz.
If 65 kHz is selected, A/D conversion becomes more accu-
rate. However, the initial value must be set on the up-
counter C0–C15 so that the up/down counter TC0–TC15
will not overflow while CR oscillation is being counted.
After an initial reset, ADCLK is set to "0".
A/D conversion START/STOP (0F1H D0)
Start A/D conversion.
When "1" is written:
A/D conversion starts
When "0" is written:
A/D conversion stops
Reading:
Valid
When "1" is written in the ADRUN, A/D conversion begins.
The register remains at "1" during A/D conversion and is set
to "0" when A/D conversion is terminated.
When "0" is written in the ADRUN during A/D conversion,
A/D conversion is paused.
ADRUN is set to "0" at initial reset, when the up/down
counter overflows or when measurement is finished.
Interrupt mask register (0ECH D0)
Select whether to mask interrupt with the A/D converter.
When "1" is written:
Enable
When "0" is written:
Mask
Reading:
Valid
The A/D converter interrupt is permitted when "1" is written
in the EIAD. When "0" is written, interrupt is masked.
After an initial reset, this register is set to "0".
ADRUN
EIAD
ADCLK
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