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參數(shù)資料
| 型號： | S-T111 |
| 英文描述： | Voltage Regulators |
| 中文描述： | 穩(wěn)壓器 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 379K |
| 代理商： | S-T111 |
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-T111 Series
Rev.1.2
_00
Operation
10
Seiko Instruments Inc.
1. Basic operation
Figure 10 shows the block diagram of the S-T111 Series.
The error amplifier compares the reference voltage (V
ref
) with V
fb
, which is the output voltage resistance-
divided by feedback resistors R
s
and R
f
.
It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
Reference voltage
circuit
VOUT
*1
*1.
Parasitic diode
VSS
VIN
R
s
R
f
Error
amplifier
Current
supply
V
ref
+
V
fb
Figure 10
2. Output transistor
The S-T111 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V
OUT
does not exceed V
IN
+
0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from the VOUT pin through a parasitic diode to the VIN pin.
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