參數(shù)資料
型號： S-24C02ADPA-11-S
廠商： Seiko Instruments Inc.
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù)： 10/23頁
文件大?。?/td> 278K
代理商： S-24C02ADPA-11-S
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2
_30
10
Seiko Instruments Inc.
S
T
A
R
T
1
0 1 0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRES
WORD ADDRESS (n)
DATA (n)
R
/
W
M
S
B
SDA LINE
ADR INC
A2A1A0
W7W6W5W4W3W2W1W0
D7D6D5D4D3D2D1D0
A
C
K
L
S
B
A
C
K
A
C
K
0
D7
D0
D7
D0
ADR INC
A
C
K
ADR INC
A
C
K
DATA (n+1)
DATA (n+x)
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
In the S-24C01A or S-24C02A, the lower 3 bits of the word address are automatically incremented
each when the EEPROM receives 8-bit write data.
Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the
lower 3 bits are rolled over and overwritten.
In the S-24C04A, the lower 4 bits at the word address are automatically incremented each when the
EEPROM receives 8 bit write data.
Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address
P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.
6.3
Acknowledgment Polling
Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.
After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are
prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device.
Accordingly, the master device transmits the start condition signal and the device address read/write
instruction code to the EEPROM (namely, the slave device) to detect the response of the slave
device. This allows users to know when the rewriting of the EEPROM is finished.
That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is
rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting
has been completed. It is recommended to use read instruction "1" for the read/write instruction
code transmitted by the master device.
6.4
Write Protection
The S-24C02A and the S-24C04A are capable of protecting the memory. When the WP pin is
connected to V
CC
, writing to 50% of the latter half of all memory area (080h to 0FFh in the S-24C02A;
100h to 1FFh in the S-24C04A) is prohibited. Even when writing is prohibited, since the controller
inside the IC is operating, the response to the signal transmitted by the master device is not available
during the time of writing (t
WR
).
When the WP pin is connected to GND, the write protection becomes invalid, and writing in all
memory area becomes available. However, when there is no need for using write protection, always
connect the WP pin to GND.
Figure 11
Page Write
相關(guān)PDF資料
PDF描述
S-24C02ADPA-TB11 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C02ADPA-TB11-1A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C02ADPA-TB11-S The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C02AFJA-11 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
S-24C02AFJA-11-1A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S-24C02ADPA-TB11 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM
S-24C02ADPA-TB11-1A 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM
S-24C02ADPA-TB11-S 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM
S-24C02ADP-TB11 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM
S-24C02ADP-TB11-1A 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM
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