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參數(shù)資料
| 型號： | S-24C01ADPA-11 |
| 廠商： | Seiko Instruments Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 278K |
| 代理商： | S-24C01ADPA-11 |
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2
_30
12
Seiko Instruments Inc.
7.2
Random Read
Random read is a mode used when the data is read from arbitrary memory addresses.
To load a memory address into the address counter inside the EEPROM, first perform a dummy write
according to the following procedures:
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0,"
following the start condition signal, it outputs the acknowledgment signal.
Next, the EEPROM receives an 8-bit length word address and outputs the acknowledgment signal. Last,
the memory address is loaded into the address counter of the EEPROM.
the EEPROM receives the write data during byte or page writing. However, data reception is not
performed during dummy write.
The memory address is loaded into the memory address counter inside the EEPROM during dummy write.
After that, the master device can read the data starting from the arbitrary memory address by transmitting
a new start condition signal and performing the same operation as that in the "Current Read."
That is, when the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal.
Next, 8-bit length data is output from the EEPROM, in synchronization with the SCL clock. The master
device does not output an acknowledgment signal and transmits the stop condition signal to finish reading.
S
T
A
R
T
1
0
1
0
W
R
I
T
E
S
T
O
P
DEVICE
ADDRESS
WORD ADDRESS (n)
R
/
W
M
S
B
SDA LINE
A2 A1A0
W7W6W5W4W3W2W1W0
A
C
K
L
S
B
A
C
K
A
C
K
0
1
0 1
0 A2 A1A0 1
D7 D6 D5 D4 D3 D2 D1 D0
DATA (n)
DUMMY WRITE
DEVICE
ADDRESS
R
E
A
D
NO ACK from
Master Device
ADR INC
S
T
A
R
T
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
Figure 13
Random Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S-24C01ADPA-11-1A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-11-S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-TB11 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-TB11-1A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-TB11-S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-24C01ADPA-11-1A | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-11-S | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-TB11 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-TB11-1A | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-TB11-S | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
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