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| 型號： | S-24C01ADPA-11-S |
| 廠商： | Seiko Instruments Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 278K |
| 代理商： | S-24C01ADPA-11-S |
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A Rev. 2.2
_30
8
Seiko Instruments Inc.
4. Acknowledgment
The unit of data transmission is 8 bits. By turning the SDA line "L," the slave device mounted on the
system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal
verifying the data reception.
When the EEPROM is rewriting, the device does not output the acknowledgment signal.
5. Device Addressing
To perform data communications, the master device mounted on the system outputs the start condition
signal to the slave device.
Next, the master device outputs 7-bit length device address and a 1-bit length
read/write instruction code onto the SDA bus.
Upper 4 bits of the device address are called the "Device Code," and set to "1010." Successive 3 bits are called the
"Slave Address." It is used to select a device on the system bus, and compared to the predetermined address value
at the address input pin (A2, A1, or A0).
When the comparison results match, the slave device outputs the acknowledgment signal during the 9th clock
cycle
.
In the S-24C04A, "A0" does not exist in the slave addresses. So, "A0" becomes "P0." "P0" is a page address bit and
is equivalent to an additional uppermost bit of the word address. Accordingly, when P0="0," the former half area
corresponding to 2 kbits (addresses from 000h to 0FFh) in the entire memory are selected; when P0="1," the latter
half area corresponding to 2 kbits (addresses from 100h to 1FFh) in all areas of the memory are selected.
Figure 8
Acknowledgment Output Timing
1
8
9
Acknow-
ledgment
Output
t
AA
t
DH
Start
Condition
SCL
(EEPROM Input)
SDA
(Master Output)
SDA
(EEPROM Output)
Figure 9
Device Address
Slave Address
1
0
1
0
A2
A1
A0
R/W
Device Code
S-24C01A
S-24C02A
MSB
LSB
1
0
1
0
A2
A1
A0
R/W
1
0
1
0
A2
A1
P0
R/W
S-24C04A
MSB
LSB
Device Code
Slave
Address
Page
Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S-24C01ADPA-TB11 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-TB11-1A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01ADPA-TB11-S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01AFJA-11 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| S-24C01AFJA-11-1A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-24C01ADPA-TB11 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-TB11-1A | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADPA-TB11-S | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADP-TB11 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
| S-24C01ADP-TB11-1A | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:CMOS 2-WIRE SERIAL EEPROM |
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