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參數(shù)資料
| 型號： | S-22S12 |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 1Kbits Non-Volatile CMOS RAM(1K位 CMOS非易失性RAM) |
| 中文描述： | 1Kbits非揮發(fā)性CMOS存儲器（每1000位的CMOS非易失性內(nèi)存） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 77K |
| 代理商： | S-22S12 |
PARALLEL NON-VOLATILE RAM
S-22 Series
Seiko Instruments Inc.
7
3. SRAM
E
2
PROM mode
3.1 Store mode
When STORE goes V
IL
(V
ILS
), the S-22 Series enters into the store mode: the SRAM data is copied to the E
2
PROM.
The original data in the SRAM is effective. Since the copied data in the E
2
PROM is non-volatile, they are retained even
if power turns off. When STORE falls, the store operation starts and finishes automatically. When store operation
starts, I/O1 to I/O4 go to high impedance and other operations are inhibited until store operation is finished and STORE
goes to high. During store operation, the CPU can access other instructions.
The store operation is inhibited if power supply voltage (V
CC
) is under V
WI
(
3.5 V).
The following two methods prevent erroneous store, caused by noise when power turns on or off:
RECALL goes V
IL
(V
ILS
) when power turns on or off (see Figure 9).
STORE connects to V
CC
with pull-up resistor.
3.2 Recall mode
When RECALL goes V
IL
(V
ILS
), the S-22 Series enters into the recall mode: the data copied into the E
2
PROM is
recopied to the SRAM. The recopied data can be read or written as SRAM data. Even if the data is copied repeatedly,
the data in the E
2
PROM does not change. Other operations are inhibited during its operation.
Figure 9 STORE inhibition period and reception period at power ON and OFF
Finish of recall operation
Store
inhibition
Store
inhibition
Store reception
t
V
CC
V
IL
*2
V
IH
*1
V
RECALL
*1
V
IHS
for the S-22S Series
*2
V
ILS
for the S-22S Series
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