參數(shù)資料
型號: S-1312A22-M5T1U3
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: FIXED POSITIVE LDO REGULATOR, PDSO5
封裝: HALOGEN FREE AND LEAD FREE, SOT-23, 5 PIN
文件頁數(shù): 7/41頁
文件大?。?/td> 523K
代理商: S-1312A22-M5T1U3
LOW CURRENT CONSUMPTION HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.1.1_00
S-1312 Series
Seiko Instruments Inc.
15
Standard Circuit
CIN
*1
CL
*2
Input
Output
GND
Single GND
VOUT
VIN
VSS
ON / OFF
*1.
CIN is a capacitor for stabilizing the input.
*2.
Ceramic capacitor of 0.22
μF or more can be used as CL.
Figure 14
Caution
The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
Condition of Application
Input capacitor (CIN) :
0.22
μF or more
Output capacitor (CL) :
0.22
μF or more (Ceramic capacitor)
Caution A general series regulator may oscillate, depending on the external components. Confirm that no
oscillation occurs in the application for which the above capacitors are used.
Selection of Input and Output Capacitors (CIN, CL)
The S-1312 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 0.22
μF or more over the entire temperature range.
When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, the capacitance must be 0.22
μF or
more.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended capacitance for an application is CIN
≥ 0.22 μF, CL ≥ 0.22 μF; however, when selecting the output
capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.
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