參數(shù)資料
型號: S-1131B20UC-N4F-TFG
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: 2 V FIXED POSITIVE LDO REGULATOR, 0.6 V DROPOUT, PDSO5
封裝: LEAD FREE, SOT-89, 5 PIN
文件頁數(shù): 5/30頁
文件大?。?/td> 407K
代理商: S-1131B20UC-N4F-TFG
HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Rev.4.0_00
S-1131 Series
Seiko Instruments Inc.
13
Operation
1. Basic operation
Figure 13 shows the block diagram of the S-1131 Series.
The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-
divided by feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
Reference voltage
circuit
VOUT
*1
*1.
Parasitic diode
VSS
VIN
Rs
Rf
Error
amplifier
Current
supply
Vref
+
Vfb
Figure 13
2. Output transistor
The S-1131 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due
to inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
相關PDF資料
PDF描述
S-1131B48UC-N5H-TFG 4.8 V FIXED POSITIVE LDO REGULATOR, 0.28 V DROPOUT, PDSO5
S-1131B39UC-N4Y-TFG 3.9 V FIXED POSITIVE LDO REGULATOR, 0.28 V DROPOUT, PDSO5
S-1131B52UC-N5L-TFG 5.2 V FIXED POSITIVE LDO REGULATOR, 0.28 V DROPOUT, PDSO5
S-1131B18UC-N4D-TFG 1.8 V FIXED POSITIVE LDO REGULATOR, 0.75 V DROPOUT, PDSO5
S-1132B15-I6T2U 1.5 V FIXED POSITIVE LDO REGULATOR, 0.58 V DROPOUT, PDSO6
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