
87
Real time clock module
88
Real time clock module
Register table
Address
Register symbol
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
Seconds
o
S 40
S 20
S 10
S 8
S 4
S 2
S 1
1
Minutes
o
M 40
M 20
M 10
M 8
M 4
M 2
M 1
2
Hours
o
H 20 P, A
__
H 10
H 8
H 4
H 2
H 1
3
Weekdays
o
W 4
W 2
W 1
4
Days
o
D 20
D 10
D 8
D 4
D 2
D 1
5
Months
o
MO 10
MO 8
MO 4
MO 2
MO 1
6
Years
Y 80
Y 40
Y 20
Y 10
Y 8
Y 4
Y 2
Y 1
7
Digital Offset
o
F 6
F 5
F 4
F 3
F 2
F 1
F 0
8
Alarm_W ; Minutes
o
WM 40
WM 20
WM 10
WM 8
WM 4
WM 2
WM 1
9
Alarm_W ; Hour
o
WH 20 WP, A
WH 10
WH 8
WH 4
WH 2
WH 1
A
Alarm_W ; Weekday
o
WW 6
WW 5
WW 4
WW 3
WW 2
WW 1
WW 0
B
Alarm_D ; Minutes
o
DM 40
DM 20
DM 10
DM 8
DM 4
DM 2
DM 1
C
Alarm_D ; Hour
o
DH 20 DP, A
__
DH 10
DH 8
DH 4
DH 2
DH 1
D
Reserved
E
Control 1
WALE
DALE
1
____
2, 24
C
___________
LEN 2
TEST
CT 2
CT 1
CT 0
F
Control 2
VDSL
VDET
X
______
ST
PON
C
___________
LEN 1
CTFG
WAFG
DAFG
0 : Always set this bit to “0”.
AC characteristics
Item
Symbol Min. Typ. Max. Unit
SCL clock frequency
fSCL
–
400 kHz
Tolerance spike time on bus
tSP
50
ns
Start condition set-up time tSU ; STA
0.6
s
Start condition Hold time
tHD ; STA
SCL “L” time
tLOW
1.3
SCL “H” time
tHIGH
0.6
SCL and SDA rise time
tr
–
0.3
SCL and SDA fall time
tf
Data set-up time
tSU ; DAT 200
ns
Data hold time
tHD ; DAT
0
Stop condition set-up time tSU ; STO 0.6
s
Bus free time
tBUF
2.0
Timing chart
Protocol
SCL
Start
Condition (s)
Start
Condition (s)
Stop
Condition (P)
tSU;STO
tSP
tHD;DAT
tSU;STA
tHD;STA
tSU;STA
tLOW
tHIGH
1/fSCL
(A)
(P)
(S)
tf
tr
(S)
tBUF
tSU;DAT
tHD;STA
Bit 7
MSB (A7)
Bit6
(A6)
Bit0
LSB
(R/W)
ACK
(A)
SDA
Block diagram
INTA
FOUT
VDD
FOE
SCL
SDA
GND
INTB
OSC
Interrupt Control
Shift Register
Time Counter
(Sec, Min, Hour, Week, Day, Month,Year)
I/O
Control
Voltage
Detect
Div.
Divider
Correc
-tion
32 kHz
Output
Control
OSC
Detect
Address
Decoder
Alarm_D Register
(Min, Hour)
Comparator_D
Comparator_W
Address
Register
Alarm_W Register
(Min, Hour, Week)