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參數(shù)資料
| 型號(hào)： | RX-4702CFB |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | REAL TIME CLOCK, PDSO10 |
| 封裝： | LEAD FREE, SON-10 |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | RX-4702CFB |
81
82
Real time clock module
Register table
RTC-4701 JE / NB : BANK0
Address
Register symbol
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
Sec
fos
S 40
S 20
S 10
S 8
S 4
S 2
S 1
1
Min
fr
Min 40
Min 20
Min 10
Min 8
Min4
Min 2
Min 1
2
Hour
fr
0
Hour 20
Hour 10
Hour 8
Hour4
Hour 2
Hour 1
3
Day of Week
fr
W 6
W 5
W 4
W 3
W 2
W 1
W 0
4
Day
fr
0
Day 20
Day 10
Day 8
Day 4
Day 2
Day 1
5
Month
fr
C
0
Month 10
Month 8
Month 4
Month 2
Month 1
6
Year
Year 80
Year 40
Year 20
Year 10
Year 8
Year 4
Year 2
Year 1
7
Minutes Alarm
AE
A-Min 40
A-Min 20
A-Min 10
A-Min 8
A-Min 4
A-Min 2
A-Min 1
8
Hours Alarm
AE
A-Hr 20
A-Hr 10
A-Hr 8
A-Hr 4
A-Hr 2
A-Hr 1
9
Day of week Alarm
AE
A-W 6
A-W 5
A-W 4
A-W 3
A-W 2
A-W 1
A-W 0
A
Day Alarm
AE
A-Day 20
A-Day 10
A-Day 8
A-Day 4
A-Day 2
A-Day 1
B
–
C
Timer setup
TE
TD1
TD0
D
Timer Couner
128
64
32
16
8
4
2
1
E
Control 1
0
TI / TP
AF
TF
AIE
TIE
F
Control 2
0
TEST
STOP
RESET
HOLD
0
RX-4702CF : BANK0
Address
Register symbol
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
B
Additional counter 1
128
64
32
16
8
4
2
1
C
Additional counter 2
fr
AC1
AC0
OVF
2048
1024
512
256
D
Control 3
FOES
TEST1
0
–
ACIE
ACE
SON
E
Control 1
0
AF
0
AIE
0
F
Control 2
0
TEST0
STOP
RESET
HOLD
0
RTC-4701 JE / NB : BANK1
Address
Register symbol
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
B
Additional counter 1
128
64
32
16
8
4
2
1
C
Additional counter 2
fr
AC1
AC0
OVF
2048
1024
512
256
D
–
E
–
F
Control 3
FOES
TEST
–
ACIE
ACE
SON
Registers 0 to A are the same in BANK0 and BANK1.
AC characteristics
(GND = 0 V, Ta = -40 °C to +85 °C)
Item
Symbol Control
VDD= 3.0V ± 10 % VDD= 5.0V ± 10 %
Unit
Min. Max. Min. Max.
CLK clock cycle
tCLK
–
600
–
350
–
ns
CLK H Pulse Width
tWH
300
175
CLK L Pulse Width
tWL
CE setup time
tCS
CE hold time
tCH
CE recovery time
tCR
400
300
Write data setup time
tDS
75
50
Write data hold time
tDH
Write data disable delay time tWZ
0
Output mode switching time tDO
Read data delay time
tRD CL = 50 pF
–
300
–
120
Output disable time
tRZ C
L
= 50 pF
RL = 10 kΩ
200
100
Rise and fall time
tRF
–
100
50
FOUT duty ratio
(32.768 kHz output)
Duty
40
60
40
60
%
Timing chart
tCH
tRF
tWL
tCLK
tDS tDH
D0
D1
D6
D7
D0
D6
D7
D0
D1
D6 D7
D0
D6
D7
tWZ
tRZ
tRD
tWH
tCS
tCR
CE
CLK
DATA
Data Read
DATA
Data Write
50 %
10 %
90 %
(Write data)
(Read data)
From here the DATA pin turns into the output mode.
(Setup code, setup address)
10 %
tDO
Block diagram
VTEMP
SOFF
Bus interface circuit
Fout controller
Divider
Temperature
Sensor
FOUT
DATA
CLK
FOE
CE
TIRQ
IRQ
AIRQ
Clock and Calendar
Timer register
Alarm register
Control register
and
System Controller
Degital Trimming register
Interrupts controller
OSC
32.768 kHz
Control line
4701JE/NB
4702CF
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