參數(shù)資料
型號(hào): RT9204GS
廠商: Richtek Technology Corporation
英文描述: Dual Regulators - Standard Buck PWM DC-DC and Linear Controller
中文描述: 雙穩(wěn)壓器-標(biāo)準(zhǔn)降壓PWM型DC - DC和線性控制器
文件頁(yè)數(shù): 11/14頁(yè)
文件大小: 199K
代理商: RT9204GS
RT9204/A
Preliminary
11
DS9204/A-08 March 2007
www.richtek.com
Input / Output Capacitor
High frequency/long life decoupling capacitors should be
placed as close to the power pins of the load as physically
possible. Be careful not to add inductance to the PCB
trace, as it could eliminate the performance from utilizing
these low inductance components. Consult with the
manufacturer of the load on specific decoupling
requirements.
The output capacitors are necessary for filtering output
and stabilizing the close loop (see the PWM loop stability).
For powering advanced, high-speed processors, it is
required to meet with the requirement of fast load transient,
high frequency capacitors with low ESR/ESL capacitors
are recommended.
Another concern is high ESR induced ripple may trigger
UV or OV protections.
Linear Regulator Driver
The linear regulator of RT9204/A was designed to drive
bipolar NPN or MOSFET pass transistor. For MOSFET
pass transistor, normally DRV need to provide minimum
V
OUT2
+VT+gate-drive voltage to keep V
OUT2
as setting
voltage. When driving MOSFET operating at 5V power
supply system, the gate-drive will be limited at 5V. In this
situation shown in Figure 5, low VT threshold MOSFET
(VT = 1V) and Vout2 setting below 2.5V were suggested.
In V
BOOT
= 12V operation condition as Figure 8, VCC is
regulated as higher to 6V providing more gate-drive for
pass MOSFET transistor, V
OUT2
can be set as
3.3V.
Figure 7
Figure 8
PWM Loop Stability
The RT9204/A is a voltage mode buck controller designed
for 5V step-down applications. The gain of error amplifier
is fixed at 35dB for simplified design.
The output amplitude of ramp oscillator is 1.6V, the loop
gain and loop pole/zero are calculated as follows:
The RT9204/A Bode plot as shown Figure 9. is stable in
most of application conditions.
Figure 9
BOOT
VCC
DRV
FBL
RT9204/A
VCC = 5V
R4
R3
+
R4<1K
V
OUT2
< 2.5V
BOOT
VCC
DRV
FBL
RT9204/A
6V
R4
R3
+
R4<1K
V
BOOT
= 12V
V
OUT2
< 3.3V
Loop Gain
40
30
20
10
1M
10k
1k
100
100k
V
OUT
= 3.3V
C
OUT
= 1500uF(33m
)
L = 2uH
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
P
O
= 2.9kHz
Z
O
= 3.2kHz
p
×
×
A
OUT
V
O
O
5
0.8
DC loop gain G = 35 dB
1.6
1
LC filter pole P =
2
LC
Error Amp pole P = 300kHz
1
ESR zero Z =
2 ESR C
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