參數(shù)資料
型號: RT9202GS
廠商: Richtek Technology Corporation
英文描述: Single Synchronous Buck PWM DC-DC Controller
中文描述: 單同步降壓PWM DC - DC控制器
文件頁數(shù): 12/14頁
文件大?。?/td> 209K
代理商: RT9202GS
RT9202
12
DS9202-09 March 2007
www.richtek.com
Figure 6
Loop Gain
40
30
20
10
1M
10k
1k
100
100k
V
OUT
= 3.3V
C
= 1500
μ
F(33m
)
L = 2
μ
H
V
OUT
= 1.5V
V
OUT
= 2.5V
V
OUT
= 3.3V
P
O
= 2.9kHz
Z
O
= 3.2kHz
Reference Voltage
Because RT9202 use a low 35dB gain error amplifier,
shown in Figure 7. The voltage regulation is dependent
on V
IN
& V
OUT
setting. The FB reference voltage of 0.8V
were trimmed at V
IN
= 5V & V
OUT
= 2.5V condition. In a
fixed V
IN
= 5V application, the FB reference voltage vs.
V
OUT
voltage can be calculated as Figure 8.
Figure 7
Figure 8
F
V
OUT
(V)
4
3.5
3
1
1.5
2
2.5
0.82
0.78
0.80
0.81
0.79
0.5
4.5
VIN = 5V
Feedback Divider
The reference of RT9202 is 0.8V. The output voltage can
be set using a resistor based divider as shown in Figure
9. Put the R1 and R2 as close as possible to FB pin and
R2 should less than 1 k
to avoid noise coupling. The C1
capacitor is a speed-up capacitor for reducing output ripple
to meet with the requirement of fast transient load.
Typically a 1nF to 0.1
μ
F is enough for C1.
Figure 9
V
IN
+
R1
C1
FB
RT9202
V
OUT
L
R2
<1K
C
OUT
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that
results in over-voltage stress on devices. Careful
component placement layout and printed circuit design
can minimize the voltage spikes induced in the converter.
Consider, as an example, the turn-off transition of the
upper MOSFET prior to turn-off, the upper MOSFET was
carrying the full load current. During turn-off, current stops
flowing in the upper MOSFET and is picked up by the
low side MOSFET or Schottky diode. Any inductance in
the switched current path generates a large voltage spike
during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes.
+
-
EA
+
-
PWM
56K
1K
+
-
FB
REP
0.8V
RAMP
1.75V
R1
R2
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