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參數(shù)資料
| 型號(hào)： | RS8235KHFD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ServiceSAR Controller |
| 中文描述： | ServiceSAR控制器 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 509K |
| 代理商： | RS8235KHFD |
Special Features:
xBR Traffic Management
TM 4.0 Service Classes
– CBR
– VBR (single, dual and CLP 0+1 leaky buckets)
– Real-time VBR
– ABR
– UBR
– GFC (controlled and uncontrolled flows)
– Guaranteed frame rate (GFR) (guaranteed
MCR on UBR VCCs)
8 Levels of priorities (8 + CBR)
Dynamic per-VCC scheduling
Multiple programmable ABR templates
(supplied by Conexant or user)
Scheduler driven by local clock for low-jitter CBR
Internal RM OAM cell feedback path
Virtual FIFO rate matching
Per-VCC MCR and ICR
Tunneling
– VP tunnels (VCI interleaving on
PDU boundaries)
– CBR tunnels (cells interleaved on UBR
with an aggregate CBR limit)
Multi-Queue Segmentation Processing
4 Transmit queues with optional priority levels
4K VCCs maximum **
AAL5 CPCS generation
AAL0 Null CPCS (optional use of PTI for
PDU demarcation)
ATM cell header generation
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (with 2-cell PDUs)
Message and streaming status modes
Variable-length transmit FIFO-CDV-host
latency matching (1 to 9 cells)
Symmetric Tx and Rx architecture
– Buffer descriptors
– Queues
User-defined field circulates back to host (32 bits)
Distributed host or SAR-shared
memory segmentation
Simultaneous segmentation and reassembly
Per-PDU control of CLP/PTI (UBR)
Per-PDU control of AAL5 UU field
Virtual Tx FIFO (PCI host)
Multi-Queue Reassembly Processing
4 reassembly queues
4K VCCs maximum **
AAL5 CPCS checking
AAL0
– PTI termination
– Cell count termination
Early packet discard, based on:
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO full
– Frame Relay DE with priority threshold
– LECID filtering for echo suppression
– Per-VCC firewalls
Dynamic channel lookup (NNI or UNI addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signaling address assignment
Message and streaming status modes
Raw cell mode (52 octet)
200 Mbps half duplex
155 Mbps full duplex (with 2-cell PDUs)
Distributed host or SAR-shared
memory reassembly
8 programmable reassembly hardware
time-outs (assignable per VCC)
Global max PDU length for AAL5
Per-VCC buffer firewall (memory usage limit)
Simultaneous reassembly and segmentation
Idle cell filtering
High-Performance Host Architecture
with Buffer Isolation
Write-only control and status
Read multiple command for data transfer
Up to 4 host clients control and status queues
Physical or logical clients
– Enables peer-to-peer architecture
Descriptor-based buffer chaining
Scatter/gather DMA
Endian neutral
Non-word (byte) aligned host buffer addresses
Automatically detects presence of Tx data
or Rx free buffers
Virtual FIFOs (PCI bursts treated as single address)
Hardware indication of BOM
Allows isolation of system resources
Status queue interrupt delay
Designer Toolkit
Evaluation module (RS8235/8251EVM)
Reference schematics
Hardware Programming Interface –
RS8235HPI reference source code (C)
RS8235 Endstation SAR
RS8235HPI Hardware
Programming Interface
The RS8235 Hardware Programming Interface (HPI)
provides a set of fully-defined software primitives to
interface with an ATM UNI port based on the RS8235
SAR. It serves as an interface point for system software
designed to configure and manage the RS8235-based
UNI without the need for detailed manipulation of hard-
ware-related structures. It thus provides a layer of abstrac-
tion from the hardware for the system designer and user.
RS8235HPI primitives are used by higher-level application
software (such as network management and device
drivers) to obtain ATM services as required by their upper
protocol layers. These primitives handle SAR resource,
control and status management.The RS8235HPI performs
functions in the following categories:
RS8235 SAR device initialization
Memory resource allocation
Resource management
Connection management (including VCC setup
and teardown, and processing status)
Segmentation/data transmission
Data reception/reassembly
Statistics gathering/error reporting
Diagnostic testing
The RS8235HPI provides a reference implementation of
these critical functions in order to shorten the development
of a production-quality, customer system specific
ATM application.
The RS8235HPI is implemented in well-documented C
source code, specifically written to be highly portable
across a multiplicity of processors, compilers and
development environments.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RS8251EVM | ServiceSAR Controller |
| RSC20-200 | ASIC |
| RSC30-300 | ASIC |
| RSC40-400 | ASIC |
| RSC50-500 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RS8250EBGC | 制造商:Conexant Systems Inc 功能描述: 制造商:Conexant Systems Inc 功能描述:ATM/SONET FRAMER, 156 Pin, Plastic, BGA |
| RS8250EVM | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ServiceSAR Controller |
| RS8251EVM | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ServiceSAR Controller |
| RS8-29754 | 制造商:Banner Engineering 功能描述:RS8-29754 SOCKET SEE NOTE |
| RS-8-30 | 制造商:Thomas & Betts 功能描述:4"SQBXCVR,STL,5CU,2-DX FL RCPT,RSD |
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