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| 型號： | RH8053GC017512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 14/81頁 |
| 文件大小： | 598K |
| 代理商： | RH8053GC017512 |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
14
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.
Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.
Figure 2. Clock Control States
HALT/Grant
Snoop
Normal
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and !HS)
or RESET#
HLT and
halt bus cycle
Snoop
serviced
Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP#
BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
V0001-00
NOTES:
halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT – HLT instruction executed
HS – Processor Halt State
QSE – Quick Start State Enabled
SGA – Stop Grant Acknowledge bus cycle issued
stop break – BINIT#, RESET#
2.2.4
Stop Grant State
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop
requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the
Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the
Normal state can be made by the deassertion of the STPCLK# signal or the occurrence of a stop
break event (a BINIT# or RESET# assertion).
The processor will return to the Stop Grant state after the completion of a BINIT# bus
initialization unless STPCLK# has been deasserted. RESET# assertion will cause the processor to
immediately initialize itself, but the processor will stay in the Stop Grant state after initialization
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