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參數(shù)資料
| 型號： | RF2968 |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | BLUETOOTHTM TRANSCEIVER |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, LCC-32 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 150K |
| 代理商： | RF2968 |
Preliminary
11-135
RF2968
Rev A13 010912
11
T
State Machine
The RF2968 state machine is clocked with a 1MHz signal which is derived from the reference oscillator. (The mark -
space ratio of this 1MHz clock and its precise frequency are not important.) The inputs and outputs for all the states are
summarized in the table below.
Table 1. State Machine Inputs and Outputs
Notes:
a.
When the inputs try to force the controller into an undefined or illegal state, the state machine will remain in its
present state (e.g., if the present state is IDLE and the inputs try to force the device to TX DATA, the chip will stay in
IDLE mode).
PD_TX goes high after a fixed delay following TXEN going high.
1
μ
s delay from the PD_PA going low to PD_TX going low.
PD_RX goes high after a fixed delay following RXEN going high.
BPKTCTL must be low to distinguish DATA SYNC from ENABLE PA.
If RXEN=1 when entering IDLE from DISABLE PA, then IDLE is held for 1
μ
s, after which the state transitions to RX
PLL WAIT.
b.
c.
d.
e.
f.
Inputs
Outputs
Previous State
Present State
a
BnPWR BXTLEN BDATA1BPKTCTL RXEN TXEN PDXTAL CLRB PDTX PDPA PDRX
X
OFF
0
X
X
X
X
X
0
0
0
0
0
OFF
PWRON WAIT
1
0
1
X
X
X
1
1
0
0
0
PWRON WAIT
HOLD XTL
1
1
1
X
0
0
1
1
0
0
0
HOLD XTL
IDLE
1
1
X
X
0
0
1
1
0
0
0
IDLE
SLEEP
1
0
X
X
0
0
0
1
0
0
0
SLEEP
WAIT XTL
1
1
X
X
0
0
1
1
0
0
0
WAIT XTL
IDLE
1
1
X
X
0
0
1
1
0
0
0
IDLE
WAIT DATA SYNC
1
1
X
0
e
0
1
1
1
1
b
0
0
WAIT DATA
DATA SYNC
1
1
X
0
e
X
1
1
1
1
0
0
DATA SYNC
ENABLE PA
1
1
X
1
X
1
1
1
1
1
0
ENABLE PA
TX DATA
1
1
X
1
X
1
1
1
1
1
0
TX DATA
DISABLE PA
1
1
X
0
X
1
1
1
0
c
0
0
DISABLE PA
IDLE
1
1
X
X
X
f
0
1
1
0
0
0
IDLE
RX PLL WAIT
1
1
X
X
1
0
1
1
0
0
1
d
RX PLL WAIT
RX DATA
1
1
X
X
1
0
1
1
0
0
1
RX DATA
IDLE
1
1
X
X
0
X
1
1
0
0
0
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