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參數(shù)資料
| 型號： | RF2617 |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 衰減器 |
| 英文描述： | LEAD, DVI-D TO DVI-D DUAL LINK, 2M; Connector type A:DVI-D; Connector type B:DVI-D; Length, lead:2m; Cable type:Shielded; Ways, No. of:24; Series:MICROCROSS RoHS Compliant: Yes |
| 中文描述： | 12 MHz - 285 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER |
| 封裝： | PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 121K |
| 代理商： | RF2617 |
10-19
RF2617
Rev B4 010717
10
I
Pin
1
Function
CDMA+
Description
CDMA balanced input pin. This pin is internally DC-biased and should
be DC-blocked if connected to a device with a DC level other than V
CC
present. A DC to connection to V
CC
is acceptable. For single-ended
input operation, one pin is used as an input and the other CDMA input
is AC-coupled to ground. The balanced input impedance is 1k
, while
the single-ended input impedance is 500
.
Interface Schematic
2
3
CDMA-
GND
Same as pin 2, except complementary input.
See pin 1.
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
FM balanced input pin. This pin is internally DC-biased and should be
DC-blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other FM input is
AC-coupled to ground. The balanced input impedance is 1.7k
, while
the single-ended input impedance is 850
.
4
FM+
5
6
7
FM-
GND
Same as pin 4, except complementary input.
See pin 4.
Same as pin 3.
IN SELECT
Selects which IF input (CDMA or FM) is used. This is a digitally con-
trolled input. A logic "high" selects the CDMA input amplifier. A logic
"low" selects the FM input amplifier. The threshold voltage is approxi-
mately 1.3V.
No connection pin. This pin is internally biased and should not be con-
nected to any external circuitry, including ground or V
CC
.
Balanced output pin. This is an open-collector output, designed to
operate into a 250
balanced load. The load sets the operating imped-
ance, but an external choke or matching inductor to V
CC
must also be
supplied in order to correctly bias this output. This bias inductor is typi-
cally incorporated in the matching network between the output and next
stage. Because this pin is biased to V
CC
, a DC-blocking capacitor must
be used if the next stage’s input has a DC path to ground.
Same as pin 9, except complementary output.
8
NC
9
OUT-
10
11
12
13
OUT+
GND
GND
VCC
See pin 9.
Same as pin 3.
Same as pin 3.
Supply Voltage pin. External bypassing is required. The trace length
between the pin and the bypass capacitors should be minimized. The
ground side of the bypass capacitors should connect immediately to
ground plane.
Same as pin 13.
14
15
16
VCC
VCC
GC
Same as pin 13.
Analog gain adjustment for all amplifiers. Valid control ranges are from
0V to 3.0V. Maximum gain is selected with 3.0V. Minimum gain is
selected with 0V. These voltages are only valid for a 4.7k
DC source
impedance.
700
BIAS
700
CDMA-
CDMA+
650
BIAS
650
FM-
FM+
20 k
IN SELECT
OUT-
OUT+
23.5 k
15 k
12.7 k
V
CC
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