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參數(shù)資料
| 型號： | RDD104 |
| 廠商： | LSI Corporation |
| 英文描述： | SELECTABLE 4 DECADE CMOS DIVIDER |
| 中文描述： | 選擇4十年的CMOS分頻器 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 25K |
| 代理商： | RDD104 |
DYNAMIC ELECTRICAL CHARACTERISTICS:
(C
L
= 50pF, Input Rise and Fall Times = 20ns except for Clock,
unless otherwise specified.)
V
DD
MIN MAX UNIT
Clock Input Frequency
4.5V
10V
0
0
0
1.5
4.0
6.0
MHz
MHz
MHz
15V
Clock Input Rise & Fall Times 4.5 to 15V - No Limit
Clock Input Rise & Fall Time,
C
L
= 15pF 10V
4.5V
-
-
140
70
ns
ns
Clock Output Propagation
Delay, C
L
= 15pF 10V
4.5V
-
-
300
150
ns
ns
Output Rise & Fall Times
10V
4.5V
-
-
400
200
ns
ns
Propagation Delay to Output
10V
4.5V
-
-
1500
750
ns
ns
Reset Pulse Width
10V
4.5V
800
400
-
-
ns
ns
Reset Removal Time
10V
4.5V
-
-
500
250
ns
ns
Reset Propagation Delay
to Output 10V
4.5V
-
-
1400
700
ns
ns
Select Input Setup Time
10V
4.5V
-
-
800
400
ns
ns
MINIMUM PARTS OSCILLATOR CIRCUIT
PIN 6
10M
PIN 5
FIGURE 2.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW
PIN 5
PIN 6
20M
10M
100pF
40pF
FIGURE 3.
PIN 5
PIN 6
39pF
10M
FIGURE 4.
TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ
56pF
50pF
20pF
CLOCK
INPUT
SIGNAL
R1
V
SS
V
DD
V
DD
5
FIGURE 5. TYPICAL INPUT
If input signals are less than V
SS
or greater than
V
DD
, a series input resistor, R1, should be used to
limit the maximum input current to 2 milliamperes.
BUFFER
+V
-V
1 OUT OF 4 SELECTOR
DECODER
8
3
7
5
4
1
2
FIGURE 6.
RDD 104 BLOCK DIAGRAM
CLOCK
GENERATOR
÷
÷
÷
÷
10
10
10
10
R
CLOCK IN
CLOCK OUT
RESET
DIVIDER SELECT-1
DIVIDER SELECT-2
6
OSCILLATOR
EXTERNAL
COMPONENTS
OUTPUT
DD
V
SS
3 STAGE INVERTING
AMPLIFIER
RDD104-011000-2
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