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參數(shù)資料
| 型號： | RD151TS502USE |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 2.30 X 2 MM, 0.50 MM PITCH, SSOP-8 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 115K |
| 代理商： | RD151TS502USE |
RD151TS502US
REJ03D0898-0100 Rev.1.00 Apr 25, 2007
Page 5 of 6
Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Figure 3.
VDD decoupling is important to reduce Jitter performance.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
8
1
7
IN
6
SEL
PDWN
5
2
3
4
C2
C1
GND GND
VDD
DIV2
OUT
R1
GND
R2
VDD
Notes:
C1 = High frequency supply decoupling capacitor.
(0.1
F recommended)
C2 = Low frequency supply decoupling capacitor.
(22
F recommended)
R1 = Match value to line impedance.
(Please use R1 if necessary)
R2 = Pull-up resistance.
(51k
recommended)
Figure 3 Recommended circuit configuration
Remark for use
Please do not use the pull-up resistance for the OUT terminal to prevent wrong operation of IC.
Please set the voltage of the PDWN terminal according to the following procedures when it is necessary to set IC
to power-down (standby) operation immediately after the start-up this IC.
1. Set the Hi level voltage when IC starts.
2. Set the Low level voltage after IC starts.
As this counter measures, we recommend the pull-up register that has been described to the above recommended
circuit to be added beforehand.
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