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參數(shù)資料
| 型號： | RD151TS501USE |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 36 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 2.30 X 2 MM, 0.50 MM PITCH, PLASTIC, VSSOP-8 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 101K |
| 代理商： | RD151TS501USE |
RD151TS501US
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 2 of 6
Block Diagram
1/M
1/N
VDD
VSS
IN
OUT
PDWN
Synthesizer
DIV
SEL
DIV2
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
Pin Descriptions
Pin name
No.
Type
Description
VDD
1,2
Power
Power supply
VSS
3
Ground
GND
OUT
4
Output
Clock signal output
PDWN
5
Input
Power-down control *
1
SEL
6
Input
Frequency select *
1
IN
7
Input
Clock signal input *
1
DIV2
8
Input
Frequency select *
1
Note:
1. LVCMOS level input. Pull-down by internal resistor (100 k
).
Power-down Function Table
PDWN
IC Operating
OUTPUT
Remark
L
Power-down
Low level
Default *
1
H
Active
Clock signal output
Note:
1. All Circuits are set stand-by condition.
Clock Frequency Table
SEL
DIV2
Output Frequency
(IN:OUT Ratio)
Remark
L
54.0 to 72.0 MHz (1:2)
Default
H
L
67.5 to 72.0 MHz (1:2.5)
*
1
L
H
27.0 to 36.0 MHz (1:1)
H
33.75 to 36.0 MHz(1:1.25)
*
1
Note:
1. In case of selection of “SEL = H”, input frequency is limited 27 to 28.8 MHz.
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