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PRODUCT SPECIFICATION
RC7108
9
Table 5. Byte 0: Functionality and frequency select register (Default = 0)
Note 1:
Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are defaulted to 0000.
*These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.
Bit
Bit 7
Description
Default
0
0- +0.25% Center Spread Spectrum
1- Down Spread Spectrum 0 to -0.5%
Bit
(2, 6:4)
Bit(2,6:4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0- frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
1- Spread Spectrum
0- Enabled
1- Tristate all outputs
CPU
100.3
100.9
105
115
120
124
133.3
133.3
140
150
66.8
70
75
83.3
90
95
SDRAM
100.3
100.9
105
115
120
124
133.3
133.3
140
150
100.2
105
112.5
124.5
90
95
PCI
33.3
33.67
35
38.33
40
41.33
44.33
33.3
35
37.5
33.4
35
37.5
41.5
30
31.67
3V66
IOAPIC
Note 1
3V66_SEL
=0
66.6
67.34
70
64*
64*
64*
64*
66.6
70
64*
66.6
70
64*
64*
60
63.34
3V66_SEL
=1
66.6
67.34
70
76.66
80
82.66
88.66
66.6
70
75
66.6
70
75
83
60
63.34
FREQ_APIC
=0
16.67
16.84
17.5
19.17
20
20.67
22.17
16.67
17.5
18.75
16.67
17.5
18.75
20.75
15
15.84
FREQ_APIC
=1
33.3
33.67
35
38.33
40
41.33
44.33
33.3
35
37.5
3.3
35
37.5
41.5
30
31.67
Bit 3
0
Bit 1
0
Bit 0
0