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參數(shù)資料
| 型號(hào)： | R5F5630ADDFP#V0 |
| 廠商： | Renesas Electronics America |
| 文件頁(yè)數(shù)： | 139/165頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU RX630 768KB FLASH 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | RX Compare Match Timer RX DMAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RX600 |
| 核心處理器： | RX |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | CAN，EBI/EMI，I²C，LIN，SCI，SPI，USB |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 78 |
| 程序存儲(chǔ)器容量： | 768KB（768K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 96K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b，14x12b，D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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R01DS0060EJ0100 Rev.1.00
Page 75 of 168
Sep 13, 2011
RX630 Group
4. I/O Registers
4.
I/O Registers
This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on
writing to registers are also given at the end.
(1)
I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
The number of access cycles indicates the number of cycles based on the specified reference clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a)
Write to an I/O register.
(b)
Read the value from the I/O register to a general register.
(c)
Execute the operation using the value read.
(d)
Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP
[R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP
[R1].W, R1
;; Next process
相關(guān)PDF資料 |
PDF描述 |
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| DF36034GFPWV | IC H8/36034 MCU FLASH 64LQFP |
| VI-244-IY-F1 | CONVERTER MOD DC/DC 48V 50W |
| VI-243-IY-F4 | CONVERTER MOD DC/DC 24V 50W |
| VI-243-IY-F3 | CONVERTER MOD DC/DC 24V 50W |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F5630ADDLC | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCUs |
| R5F5630ADDLC#U0 | 制造商:Renesas Electronics Corporation 功能描述:RX630 768KB/96KB LGA177 CAN 100MHZ - Trays |
| R5F5630ADDLK | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCUs |
| R5F5630ADDLK#U0 | 制造商:Renesas Electronics Corporation 功能描述:RX630 768KB/96KB LGA145 CAN 100MHZ - Trays |
| R5F5630BCDBG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Renesas MCUs |
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