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參數(shù)資料
| 型號(hào)： | R5107G521A-TR |
| 廠商： | RICOH COMPANY LTD |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 2.90 X 4 MM, 0.65 MM PITCH, SSOP-8 |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大?。?/td> | 392K |
| 代理商： | R5107G521A-TR |
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R5107G(Preliminary)
9
Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to TW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset holding time and the external capacitor value.
tWD(s) = 3.1*10
6× C (F)
tWR(s)=tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the
next reset hold time RESETB pin outputs "L".
After starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse
is input during the time period "TWDI", the clock pulse is ignored.
TWDI[s]=TWD/10
Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation describes the
relation between the capacitance value and the released delay time (tpLH).
tpLH(s)=3.7
×10
6× C(F)
Note that the temperature dependence graph in the typical characteristics does not contain the temperature characteristics
of the external capacitor.
When the VDD voltage becomes equal or lower than -VDET, discharge of the capacitor connected to CD pin starts. In case
that the discharge is not enough, if the VDD voltage returns equal or more than (+VDET), the delay time tpLH will be
shorter than expected.
Minimum Operating Voltage (VINL)
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB pin being
0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100k
in the case of the Nch open-drain output type.
Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be dominant by the
voltage detector's operation. Therefore, if the equal or more than the detector threshold level is input, RESETB outputs "H"
regardless the clock pulse. INH pin is pulled up with a resistor (TYP. 110k
) internally.
Manual Reset Function
By setting MR pin as "L", the output of RESETB can be forced to set "L". After pull-down the MR pin to "L", the delay
time (DMR) to the output "L" from RESETB is 1us as maximum. MR pin is pulled-up via the built-in resister. (Typ.
110k
). If MR pin voltage> VIN voltage, a current flows into MR pin. However, the current value is limit by the pull-up
resister, therefore there is not bad impact on the operation. When the "L" signal is input to MR pin, the discharge of CD pin
capacitor (CCD) starts. If the term of "L" for MR pin is short, CCD will not be discharged enough. As a result, the delay
time after setting "H" for MR pin will be shorter than expected. Because of this, confirm the operation under the same
conditions as users' applications. For example, in case of CCD is set at 0.1uF, and the condition to maintain the delay time
value after MR pin's returning to "H", is described as the minimum "L" term of MR pin, or 150us.
RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
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