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參數(shù)資料
| 型號： | R1LP0408CSC-7LC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, REVERSE, TSOP2-32 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 110K |
| 代理商： | R1LP0408CSC-7LC |
R1LP0408C-C Series
Rev.2.00, May.26.2004, page 12 of 12
Low VCC Data Retention Characteristics
(Ta =
20 to +70°C)
Parameter
Symbol
Min Typ
Max Unit Test conditions*
3
VCC for data retention
VDR
2
V
CS#
≥ VCC 0.2 V, Vin ≥ 0 V
to +70
°C
ICCDR
8
A
VCC = 3.0 V, Vin
≥ 0 V
to +40
°C
ICCDR
1.0*
2
3
A
CS#
≥ VCC 0.2 V
5SC
to +25
°C
ICCDR
0.8*
1
3
A
to +70
°C
ICCDR
16
A
to +40
°C
ICCDR
1.0*
2
10
A
Data
retention
current
7LC
to +25
°C
ICCDR
0.8*
1
10
A
Chip deselect to data retention time
tCDR
0
ns
See retention waveform
Operation recovery time
tR
tRC*
4
ns
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25
°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40
°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS# Controlled)
V
CC
4.5 V
2.2 V
0 V
CS#
t
CDR
t
R
CS#
≥ V
CC – 0.2 V
V
DR
Data retention mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R1LP0408CSC-7LI | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Wide Temperature Range Version 4 M SRAM (512-kword 】 8-bit) |
| R1LP0408CSP5SC | 制造商:RENESAS 功能描述:Pb Free |
| R1LP0408CSP-5SC | 制造商:Renesas Electronics Corporation 功能描述:4M SRAM 制造商:Renesas Electronics 功能描述:512k~8 55ns 5V 32SOP Tube |
| R1LP0408CSP-5SC#B0 | 功能描述:IC SRAM 4MBIT 55NS 32SOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
| R1LP0408CSP5SC#S0 | 制造商:Renesas Electronics Corporation 功能描述: |
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