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參數(shù)資料
| 型號(hào)： | QL3060-3PQ208I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大小： | 181K |
| 代理商： | QL3060-3PQ208I |
7-55
QL3060 - pASIC 3 FPGATM
AC Characteristics at VCC = 3.3V, TA = 25
°C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Input-Only/Clock Cells
Notes:
[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°C. Multiply
by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.
[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing
analysis of your particular design.
Symbol
Parameter
Propagation Delays (ns)
Fanout [5]
1234
8
tPD
Combinatorial Delay [6]
1.4
1.7
1.9
2.2
3.2
tSU
Setup Time [6]
1.7
tH
Hold Time
0.0
tCLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI
Clock High Time
1.2
tCWLO
Clock Low Time
1.2
tSET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
tRW
Reset Width
1.8
Symbol
Parameter
Propagation Delays (ns)
Fanout [5]
12348
12
24
tIN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
tINI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
tISU
Input Register Set-Up Time
3.1
tIH
Input Register Hold Time
0.0
tlCLK
Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
tlRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
tlESU
Input Register clock Enable Set-Up Time
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
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