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參數(shù)資料
| 型號(hào)： | QL3006-1PFN100C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MO-136, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/49頁(yè) |
| 文件大?。?/td> | 885K |
| 代理商： | QL3006-1PFN100C |
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2005 QuickLogic Corporation
www.quicklogic.com
1
Device Highlights
High Performance & High Density
Up to 60,000 usable PLD gates with up to
316 I/Os
300 MHz 16-bit counters, 400 MHz datapaths
0.35 m four-layer metal non-volatile CMOS
process for smallest die sizes
Easy to Use/Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O cells with individually controlled registered
input path and output enables
Up to 316 I/O Pins
Up to 308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Up to eight high-drive input/distributed network
pins
Up to Eight Low-Skew Distributed
Networks
Two array clock/control networks are available to
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
Up to six global clock/control networks are
available to the logic cell; F1, clock, set, and reset
inputs and the data input, I/O register clock,
reset, and enable inputs as well as the output
enable control — each can be driven by an input-
only pin, I/O pin, any logic cell output, or I/O cell
feedback
High Performance
Input + logic cell + output total delays under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
Figure 1:
Up to 1,584 pASIC 3 Logic Cells
pASIC 3 FPGA Family Data Sheet
Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High
Performance and High Density
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL3006-1PFN100I | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| QL3006-1PFN100M | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| QL3006-2PFN100C | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| QL3006-2PFN100I | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| QL3006-2PFN100M | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL3012 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density |
| QL3012-0PF100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL3012-0PF100C-5224 | 制造商:QuickLogic Corporation 功能描述:QLGQL3012-0PF100C-5224 QL3012-0PF100C-52 |
| QL3012-0PF100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL3012-0PF100I-5762 | 制造商:QuickLogic Corporation 功能描述: |
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