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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 37/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
PIN CONNECTION CONSIDERATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-5
Other suggestions for PCB layout in which the QADC is employed include:
Analog ground must be low impedance to all analog ground points in the circuit.
Bypass capacitors should be as close to the power pins as possible.
The analog ground should be isolated from the digital ground. This can be done
by cutting a separate ground plane for the analog ground.
Non-minimum traces should be utilized for connecting bypass capacitors and fil-
ters to their corresponding ground/power points.
Minimum distance for trace runs when possible.
5.4 Accommodating Positive/Negative Stress Conditions
Positive or negative stress refers to conditions which exceed nominally defined oper-
ating limits. Examples include applying a voltage exceeding the normal limit on an in-
put (for example, voltages outside of the suggested supply/reference ranges) or
causing currents into or out of the pin which exceed normal limits. QADC specific con-
siderations are voltages greater than V
DDA
, V
RH
or less than V
SSA
applied to an analog
input which cause excessive currents into or out of the input. Refer to
APPENDIX A
ELECTRICAL CHARACTERISTICS
for more information on exact magnitudes.
Both stress conditions can potentially disrupt conversion results on neighboring inputs.
Parasitic devices, associated with CMOS processes, can cause an immediate disrup-
tive influence on neighboring pins. Common examples of parasitic devices are diodes
to substrate and bipolar devices with the base terminal tied to substrate (V
SSI
/V
SSA
ground). Under stress conditions, current introduced on an adjacent pin can cause er-
rors on adjacent channels by developing a voltage drop across the adjacent external
channel source impedances.
Figure 5-4
shows an active parasitic bipolar when an input pin is subjected to negative
stress conditions. Positive stress conditions do not activate a similar parasitic device.
Figure 5-4 Input Pin Subjected to Negative Stress
The current out of the pin (I
OUT
) under negative stress is determined by the following
equation:
QADC PAR STRESS CONN
R
STRESS
R
ADJACENT
ADJACENT
PINS
NEGATIVE
STRESS
VOLTAGE
10K
VDD
PIN UNDER
STRESS
PARASITIC
DEVICE
I
OUT
I
IN
+
F
Freescale Semiconductor, Inc.
n
.
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