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參數(shù)資料
| 型號： | PXA250 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel-R PXA250 and PXA210 Applications Processors |
| 中文描述： | 英特爾- R的PXA250和PXA210應用處理器 |
| 文件頁數(shù)： | 38/46頁 |
| 文件大?。?/td> | 431K |
| 代理商： | PXA250 |
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PXA250 and PXA210
—
Electrical, Mechanical, and Thermal Specification
38
Datasheet
4.6.5
Sleep Mode Timing
Sleep Mode is internally asserted, it and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 7,
“
Sleep Mode Timing
”
on page 38 and detailed in Figure 16,
“
Sleep
Mode Timing Specifications
”
on page 39 is the required timing parameters for Sleep Mode.
Table 15. GPIO Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tA_GP[1]
Minimum assert time of GP[1]1 in
3.6864MHz input clock cycles
4
-
cycles
tDHW_OUT_A
Delay between GP[1] Asserted and
nRESET_OUT Asserted in 3.6864MHz
input clock cycles
6
8
cycles
tDHW_OUT
Delay between nRESET_OUT asserted
and nRESET_OUT deasserted, Run or
Turbo Mode2
5
28
s
tDHW_OUT_F
Delay between nRESET_OUT asserted
and nRESET_OUT deasserted, during
Frequency Change Sequence3
5
380
s
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check
the state of GP[1] before configuring as a Reset to ensure no spurious reset is generated.
2. Time is 512*N Processor Clock Cycles plus up to 4 cycles of the 3.6864MHz input clock.
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the
assertion of GPIO Reset. The Lock Detector has a maximum time of 350
μ
s plus synchronization.
Figure 7. Sleep Mode Timing
GP[x]
PWR_EN
VCC
nVDD_FAULT
nRESET_OUT
t
DSM_OUT
Note: nBATT_FAULT must be high or Cotulla will not exit Sleep Mode
will not exit Sleep Mode.
t
A_GP[x]
t
D_PWR_R
t
D_PWR_F
t
D_F
A UL T
t
DSM_VCC
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