
8
Data Device Corporation
www.ddc-web.com
PWR-82340/PWR-82342
H-06/05-0
SHUT-DOWN INPUT (VSD)
Pin 15 (VSd) provides a digital shut-down input, which allows the
user to completely turn off both the upper and lower output tran-
sistors in both phases. Application of a logic '1' to the VSd input
will latch the Digital Control/Protection circuitry thereby turning
off all output transistors. The Digital Control/Protection circuitry
remains latched in the off state and will not respond to signals on
the VL or VU inputs while the VSd has a logic '1' applied. When
the user or the sense circuitry (as in FIGURE 10) returns the VSd
input to a logic '0,' and then the user sets the VL and VU inputs
to a logic '0' the output of the Digital Control/Protection circuitry
will clear the internal latch. When the next rising edge (see FIG-
URE 9) occurs on the VL or VU digital inputs, the output transis-
tors will respond to the corresponding digital input. This feature
can be used with external current limit or temperature sense cir-
cuitry to disable the drive if a fault condition occurs (see FIGURE
10).
INTERNAL PROTECTION CIRCUITRY
The hybrid contains digital protection circuitry, which prevents in-
line transistors from conducting simultaneously. This, in effect,
would short circuit the power supply and would damage the out-
put stage of the hybrid. The circuitry allows only proper input sig-
nal patterns to cause output conduction. Figure 9 and Table 3
(see page 13) show these timing relationships. If an improper
input requested that the upper and lower transistors of the same
phase conduct together, the output would be a high impedance
until removal of the illegal code from the input of the PWR- 82340
or PWR-82342. A dead time of 500 nsec minimum should still be
maintained between the signals at the VU and Vl pins; this
ensures the complete turn off of any transistor before turning on
its associated in-line transistor.
1
0
1
0
1
0
1
0
1
0
H
Z
L
H
Z
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t sd
V Sd
V OA
H
Z
L
1
0
V UA
V UB
V LA
V LB
V Sd
V OA
V OB
FIGURE 9. SHUT-DOWN (VSD) TIMING RELATIONSHIPS
FIGURE 10. FUNCTIONAL SHUT-DOWN INPUT USED WITH CURRENT-SENSING CIRCUITRY
Rb
VCC
INPUT COMMANDS
14
6
9
8
3
11
MOTOR
5
12
PWR-82340/342
13
UC 1637
PWM
A
B
OUT
VELOCITY
COMMAND
16
17
2
7,18
4
1
VSd
15
CURRENT
SENSE
CIRCUITRY
THERMAL SENSE
INPUT
R SENSE