參數資料
| 型號： | PT7C4307WEX |
| 廠商： | Pericom |
| 文件頁數： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC ALARM NVSRAM 8SOIC |
| 標準包裝： | 1 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出 |
| 存儲容量： | 56B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | PT7C4307WEXDKR |
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PT0206(08/09)
Ver: 3
7
Data Sheet
PT7C4307
Real-time Clock Module (I
2C Bus)
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Dates
0
D20
D10
D8
D4
D2
D1
04
(default)
0
Undefined Undefined Undefined Undefined Undefined Undefined
Months
0
M10
M8
M4
M2
M1
05
(default)
0
Undefined Undefined Undefined Undefined Undefined
Years
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
06
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
I
2C Bus Interface
Overview of I
2C-BUS
The I
2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I
2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I
2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Fig 1. System configuration
Master
MCU
Slave
RTC
Other Peripheral
Device
Vcc
SDA
SCL
Note: When there is only one master, the MCU is ready for driving SCL to "H" and R
P of SCL may not required.
R
P
R
P
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