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參數(shù)資料
| 型號： | PT7A7521PE |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, DIP8 |
| 封裝： | LEAD FREE, MS-001BA, DIP-8 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 411K |
| 代理商： | PT7A7521PE |
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PT0082(10/10)
Ver: 7
3
Data Sheet
PT7A7511-15/7521-25/7531-35
P Supervisor Circuits
Pin Configuration
Top View
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
WDO
RESET
WDI
PFO
PT7A7511P-7515P
PT7A7511W-7515W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
WDO
RESET
WDI
PFO
PT7A7521P-7525P
PT7A7521W-7525W
8-Pin PDIP/8-Pin SOIC
1
2
3
4
8
7
6
5
MR
V CC
GND
PFI
RESET
NC
PFO
PT7A7531P-7535P
PT7A7531W-7535W
8-Pin PDIP/8-Pin SOIC
Pin Description
Pin
Type
Description
MR
I
Manual-Reset: triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250mA pull-
up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
VCC
Power
Supply Voltage.
GND
Ground
Ground Reference for all signals.
PFI
I
Power-Fail Voltage Monitor Input. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND
or Vcc when not used.
PFO
O
Power-Fail Output: it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high.
WDI
I
Watchdog Input: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO
goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog
feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-stated, or WDI sees a
rising or falling edge.
RESET
O
Reset Output pulses: low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to
high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
WDO
O
Watchdog Output: pulls low when the internal watchdog timer finishes its 1.6sec count and does not go
high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc
is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum
pulse width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay.
RESET
O
The inverse of RESET, active high. Whenever RESET is high, RESET is low.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PT7A7522 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4.38V Reset Active High Supervisor? |
| PT7A7523 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.08V Reset Active High Supervisor? |
| PT7A7524 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.93V Reset Active High Supervisor? |
| PT7A7525 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.63V Reset Active High Supervisor? |
| PT7A7526 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.32V Reset Active Low Supervisor? |
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