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PT0082(10/10)

Ver: 7

4

The PT75xx family can assert reset output during power-up, power-down and brownout conditions for

P system, detect power

failure or low-battery conditions with a 1.25V threshold detector and have watchdog functions. Refer to Function Table of

PT7A75xx Family for their individual features. The typical application see Figure 4.

The supervisory circuits can assert reset for a microprocessor during power-up, power-down and brownout to prevent code

execution errors.

On power-up, once Vcc reaches about 1.2V, RESET is a guaranteed logic low of 0.4V or less. As Vcc rises, RESET stays low.

When Vcc rises above the reset threshold, an internal timer releases RESET after about 200ms. RESET pulses low whenever Vcc

drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the

pulse continues for at least another 140ms. On power-down, once Vcc falls below the reset threshold, RESET stays low and is

guaranteed to be 0.4V or less until Vcc drops below 1.0V.

The PT7A752x and PT7A753x active-high RESET output is simply the inverse of the RESET output, and is guaranteed to be

valid with Vcc down to 1.2V. Some

Ps, such as Intel’s 80C51, require an active-high reset pulse.

The watchdog circuit monitors the

P activity. If the P does not toggle the watchdog input (WDI) within 1.6sec and WDI is not

in high impedance, WDO goes low. As long as RESET is asserted or the WDI input is in high impedance, the watchdog timer will

stay cleared and will not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as

short as 50ns can be detected.

Typically, WDO will be connected to the non-maskable interrupt input (NMI) of a

P. When VCC drops below the reset

threshold, WDO will go low whether or not the watchdog timer has timed out yet. Normally this would trigger an NMI interrupt,

but RESET goes low simultaneously, and thus overrides the NMI interrupt. If WDI is left unconnected, WDO can be used as a

low-line output. Since floating WDI disables the internal timer, WDO goes low only when VCC falls below the reset threshold,

thus functioning as a low-line output.

The manual-reset input (MR) allows reset to be triggered by a push button switch. The switch is effectively debounced by the

140ms minimum reset pulse width. MR is TTL/CMOS logic compatible, so it can be driven by any logic reset output.

The power-fail comparator will send out a Low signal once detects a voltage lowered than 1.25V. It can be used for various

purposes because its output and non-inverting input are not internally connected. The inverting input is internally connected to a

1.25V reference..

DC Linear

Regulator

Vcc

PFI

WDI

Vcc

RESET

I/O Line

NMI

Interrupt

IN

OUT

RESET

WDO

PFO

MR