參數(shù)資料
型號: PSD954F2V
廠商: 意法半導體
元件分類: 基準電壓源/電流源
英文描述: Advanced PFC/PWM Combination Controllers 20-PDIP -40 to 105
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 15/94頁
文件大?。?/td> 476K
代理商: PSD954F2V
Preliminary Information
PSD9XX Family
Pin Name
Pin*
(PLCC)
Type
Description
CNTL2
49
I
This pin can be used to input the PSEN (Program Select
Enable) signal from any MCU that uses this signal for code
exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This
port is connected to the PLDs.
Reset
48
I
Active low reset input. Resets I/O Ports and some of the
configuration registers. Must be active at power up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. General Purpose PLD outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for
A[0:3] when using an 80C51XA in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed
address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
Note:
PA0-3 can only output CMOS signals with an option
for high slew rate. However, PA4-7 can be configured as
CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
I/O
These pins make up Port B. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. General Purpose PLD outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
Note:
PB0-3 can only output CMOS signals with an option
for high slew rate. However, PB4-7 can be configured as
CMOS or Open Drain Outputs.
52
51
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. TMS Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. TCK Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
11
相關(guān)PDF資料
PDF描述
PSD954F2V-12MI Advanced PFC/PWM Combination Controllers 20-PDIP -40 to 105
PSD954F2V-90J Advanced PFC/PWM Combination Controllers 20-SOIC -40 to 105
PSD954F2V-90M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2V-12JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2 Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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