參數(shù)資料
型號： PSD954F2
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 64/94頁
文件大?。?/td> 476K
代理商： PSD954F2
PSD9XX Family
Preliminary Information
60
Port C Pin
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TMS
TCK
TSTAT
TERR
TDI
TDO
Description
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Table 34. JTAG Port Signals
The
PSD9XX
Functional
Blocks
(cont.)
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 μs) time.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All
memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
*
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
**
Port Configuration
MCU I/O
PLD Output
Power On Reset
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Address Out
Data Port
Tri-stated
Tri-stated
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Cleared to
“
0
”
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Warm Reset
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Power Down Mode
Unchanged
Unchanged
PMMR0, 2
VM Register*
All other registers
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
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PSD954F2-90J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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PSD954F2V-90J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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