參數(shù)資料
型號: PSD954F2-70M
廠商: 意法半導體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數(shù): 18/94頁
文件大小: 476K
代理商: PSD954F2-70M
PSD9XX Family
Preliminary Information
14
Table 7 shows the offset addresses to the PSD9XX registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD9XX registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
8.0
PSD9XX
Register
Description
and Address
Offset
Register Name Port A Port B Port C Port D Other*
Description
Data In
00
01
10
11
Reads Port pin as input,
MCU I/O input mode
Control
02
03
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Data Out
04
05
12
13
Direction
06
07
14
15
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Drive Select
08
09
16
17
Flash Protection
C0
Read only – Flash Sector
Protection
Secondary Flash
Protection
Read only – PSD Security
and Secondary Flash
Sector Protection
C2
PMMR0
B0
Power Management
Register 0
PMMR2
B4
Power Management
Register 2
Page
E0
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
VM
E2
Table 7. Register Address Offset
*
Other registers that are not part of the I/O ports.
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