參數(shù)資料
型號： PSD954F2-70J
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 49/94頁
文件大小： 476K
代理商： PSD954F2-70J
Preliminary Information
PSD9XX Family
45
The
PSD9XX
Functional
Blocks
(cont.)
Control
Register
Setting
at Run-Time
Direction
Register
Setting
at Run-Time
Defined In
PSDsoft
Mode
MCU I/O
Declare pins only
0
1= output,
0= input,
PLD I/O
Logic or chip
select equations
NA
Data Port
(Port A)
Selected for MCU
with non-mux bus
NA
NA
Address Out
(Port A,B)
Declare pins only
1
1
Address In
(Port A,B,C,D)
Declare pins only
NA
NA
JTAG ISP
Declare pins only
NA
NA
Table 21. Port Operating Mode Settings
*
NA = Not Applicable
9.4.2.1 MCU I/OMode
In the MCU I/O Mode, the microcontroller uses the PSD9XX ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD9XX are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register. See the subsection on the Direction Register in the “Port
Registers” section. When the pin is configured as an output, the content of the Data Out
Register drives the pin. When configured as an input, the microcontroller can read the port
input through the Data In buffer. See Figure 19.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/OMode
The PLD I/O Mode uses a port as an input to the PLDs, and/or as an output from the
GPLD. The corresponding bit in the Direction Register must not be set to ‘1’ if the pin is
defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified in PSDsoft by
declaring the port pins, and then specifying an equation in PSDsoft.
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