參數(shù)資料
型號(hào)： PSD935F1V-A-12B81
廠商： 意法半導(dǎo)體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
文件頁(yè)數(shù)： 2/91頁(yè)
文件大?。?/td> 488K
代理商： PSD935F1V-A-12B81
PSD935G2
PSD9XX Family
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
PA0-PA7
51-58
I/O
Port A, PA0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port
Drain
2. GPLD output.
3. Input to the PLD.
PB0-PB7
61-68
I/O
Port B, PB0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. GPLD output.
3. Input to the PLD.
PC0-PC7 41-48
I/O
Port C, PC0-7. This port is pin configurable and has multiple
CMOS
functions:
or Slew
1. MCU I/O — standard output or input port.
Rate
2. External chip select (ECS0-7) output.
3. Input to the PLD.
PD0
79
I/O
Port D pin PD0 can be configured as:
CMOS
1. ALE or AS input — latches addresses on ADIO0-15 pins
or Open
2. AS input — latches addresses on ADIO0-15 pins on the
Drain
rising edge.
3. Input to the PLD.
4. Transparent PLD input.
PD1
80
I/O
Port D pin PD1 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD.
Drain
3. CLKIN clock input — clock input to the GPLD
Micro
Cells, the APD power down counter and GPLD
AND Array.
PD2
1
I/O
Port D pin PD2 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD.
Drain
3. CSI input — chip select input. When low, the CSI enables
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
PD3
2
I/O
Port D pin PD3 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD.
Drain
PE0
71
I/O
Port E, PE0. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TMS input for JTAG/ISP interface.
PE1
72
I/O
Port E, PE1. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TCK input for JTAG/ISP interface (Schmidt Trigger).
PE2
73
I/O
Port E, PE2. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDI input for JTAG/ISP interface.
Table 5.
PSD935G2
Pin
Descriptions
(cont.)
9
相關(guān)PDF資料
PDF描述
PSEC-01-12-01-01-L-RA 14 CONTACT(S), FEMALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER, SOCKET
PSEC-01-12-02-01-L-RA 15 CONTACT(S), FEMALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER, SOCKET
PSEC-01-12-02-01-S-RA 15 CONTACT(S), FEMALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER, SOCKET
PSEC-01-12-02-01-T-RA 15 CONTACT(S), FEMALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER, SOCKET
PSEC-01-12-04-01-L-RA 17 CONTACT(S), FEMALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER, SOCKET
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