參數(shù)資料
型號(hào)： PSD934F2V-20JI
廠商： 意法半導(dǎo)體
英文描述： Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 32/94頁
文件大?。?/td> 476K
代理商： PSD934F2V-20JI
The
PSD9XX
Functional
Blocks
(cont.)
Level 1
SRAM, I/O
Level 2
Secondary Flash Memory
Highest Priority
Lowest Priority
Level 3
Main Flash Memory
Figure 5. Priority Level of Memory and I/OComponents
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family have separate address spaces for code memory
(selected using PSEN) and data memory (selected using RD). Any of the memories
within the PSD9XX can reside in either space or both spaces. This is controlled through
manipulation of the VM register that resides in the PSD
’
s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and Flash in Data Space at boot, and Boot
Block in Program Space at boot, and later swap Boot Block and Flash. This is easily done
with the VM register by using PSDsoft to configure it for boot up and having the microcon-
troller change it when desired.
Table 13 describes the VM Register.
Bit 7*
Bit 6*
Bit 5*
Bit 4
FL_Data Boot_Data
Bit 3
Bit 2
FL_Code
Bit 1
Bit 0
Boot_Code SRAM_Code
*
*
*
0 = RD
can
’
t
access
Flash
0 = RD
can
’
t
access
Secondary
Flash
0 = PSEN
can
’
t
access
Flash
0 = PSEN
can
’
t
access
Secondary
Flash
0 = PSEN
can
’
t
access
SRAM
*
*
*
1 = RD
access
Flash
1 = RD
access
Secondary
Flash
1 = PSEN
access
Flash
1 = PSEN
access
Secondary
Flash
1 = PSEN
access
SRAM
Table 13. VM Register
NOTE:
Bits 5-7 are not used, should set to
“
0
”
.
PSD9XX Family
Preliminary Information
28
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