參數(shù)資料
型號(hào): PSD934F2V-15J
廠(chǎng)商: 意法半導(dǎo)體
英文描述: Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 61/94頁(yè)
文件大小: 476K
代理商: PSD934F2V-15J
Preliminary Information
PSD9XX Family
57
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
PLD
PLD
Turbo
*
APD
Enable
*
Array clk
1 = off
1 = off
1 = on
Table 31. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
**
*
Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
*
**
The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***
Subsequent reset pulses will not clear the registers.
The
PSD9XX
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
PLD
**
array
CNTL2
1 = off
Bit 3
PLD
**
array
CNTL1
1 = off
Bit 2
PLD
**
array
CNTL0
1 = off
Bit 1
Bit 0
*
PLD
array
DBE
1 = off
PLD
array
ALE
1 = off
*
*
PMMR2
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
*
*
Unused bits should be set to 0.
**
Refer to Table 17 the signals that are blocked on pins CNTL0-2.
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