參數(shù)資料
型號(hào): PSD934F2-90JI
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 11/94頁
文件大小: 476K
代理商: PSD934F2-90JI
Preliminary Information
PSD9XX Family
PSD9XX
Architectural
Overview
(cont.)
5.4 I/OPorts
The PSD9XX has 27 I/O pins divided among four ports (Port A, B, C, and D). Each
I/O pin can be individually configured for different functions. Ports A, B, C and D can
be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port C for In-System Programming (ISP).
Port A can also be configured as a data port for a non-multiplexed bus.
5.5 Microcontroller Bus Interface
The PSD9XX easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond
to the microcontroller’s control signals, which are also used as inputs to the PLDs. Section
9.3.5 contains microcontroller interface examples.
5.6 JTAG Port
In-System Programming can be performed through the JTAG pins on Port C. This serial
interface allows complete programming of the entire PSD9XX device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) are
enabled on Port C when selected or when a device is blank. Table 3 indicates the JTAG
signals pin assignments.
Port C Pins
JTAG Signal
PC0
PC1
PC3
PC4
PC5
PC6
TMS
TCK
TSTAT
TERR
TDI
TDO
Table 3. JTAG Signals on Port C
7
相關(guān)PDF資料
PDF描述
PSD934F2-90M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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