參數(shù)資料
型號(hào)： PSD934F2-90J
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 35/94頁
文件大?。?/td> 476K
代理商： PSD934F2-90J
Preliminary Information
PSD9XX Family
31
The
PSD9XX
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD9XX. After specifying the
chip selects or logic equations for the PLDs in PSDsoft, the logic is programmed into the
device and available upon power-up.
The PSD9XX contains two PLDs: the Decode PLD (DPLD), and the General Purpose PLD
(GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The GPLD can be used to generate external chip selects, control signals or logic functions.
The GPLD has 19 outputs that are connected to Ports A, B and D.
The AND array is used to form product terms. These product terms are specified using
PSsoft. An Input Bus consisting of 57 signals is connected to the PLDs. The signals are
shown in Table 15. The complement of the 57 signals are also available as input to the
AND array.
Input Source
Input Name
Number
of Signals
MCU Address Bus
MCU Control Signals
Reset
Power Down
Port A Input
Port B Input
Port C Input
Port D Inputs
Page Register
Flash Programming Status Bit
A[15:0]
*
CNTL[2:0]
RST
PDN
PA[7-0]
PB[7-0]
PC[7-0]
PD[2:0]
PGR(7:0)
Rdy/Bsy
16
3
1
1
8
8
8
3
8
1
Table 15. DPLD and GPLD Inputs
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD9XX can minimize power consumption by switching off when inputs
remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off
(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs
are changing. Turbo-off mode increases propagation delays while reducing power
consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
相關(guān)PDF資料
PDF描述
PSD934F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD934F2-90M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 2M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD834F2V-15M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD935G2-90U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 TQFP-80 5V 4M 90N RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD935G2V-90U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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