參數(shù)資料
型號： PSD4235F2V-12B81I
廠商： 意法半導體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設的16位微控制器
文件頁數(shù)： 47/93頁
文件大小： 503K
代理商： PSD4235F2V-12B81I
PSD4000 Series
Preliminary Information
48
Control
Direction
VM
Defined In
Register
Mode
PSDsoft
Setting
Declare
0
1 = output,
MCU I/O
pins only
(Note 1)
0 = input
NA
Declare pins
PLD I/O
and logic or chip
NA
select equations
Data Port
Selected for
(Port F, G)
MCU with
NA
non-mux bus
Address Out
Declare
11
NA
(Port E, F, G)
pins only
Address In
Declare pins
(Port A,B,C,D,F)
NA
JTAG ISP
Declare pins
NA
only
MCU Reset
Specify pin
NA
Mode
logic level
Table 17. Port Operating Mode Settings
*NA = Not Applicable
NOTE: 1. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD4000 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing
to the corresponding bit in the Direction Register. See the subsection on the Direction
Register in the “Port Registers” section. When the pin is configured as an output, the
content of the Data Out Register drives the pin. When configured as an input, the
microcontroller can read the port input through the Data In buffer. See Figure 20.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro
Cells, and/or
as an output from the GPLD. The corresponding bit in the Direction Register must not be
set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified
in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
The
PSD4000
Functional
Blocks
(cont.)
相關PDF資料
PDF描述
PSD835F1V-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
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PSD835F1V-12JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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相關代理商/技術參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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