參數(shù)資料
型號(hào): PS399ESEE
廠商: Pericom
文件頁(yè)數(shù): 11/11頁(yè)
文件大小: 0K
描述: IC MULTIPLEXER DUAL 4X1 16SOIC
產(chǎn)品變化通告: Product Discontinuation Notice 11/Feb/2008
標(biāo)準(zhǔn)包裝: 48
功能: 多路復(fù)用器
電路: 2 x 4:1
導(dǎo)通狀態(tài)電阻: 100 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 3 V ~ 15 V,±3 V ~ 8 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
9
PS8185F
09/28/04
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PS398/PS399
Precision 8-Ch, Diff. 4-Ch, 17V Analog Multiplexers
Figure 8. NO/COM Capacitance
Figure 9. Overvoltage protection is accomplished using two
external blocking diodes or two current limiting resistors.
V+
Positive Supply
COM
NO
Vg
V-
Applications
OvervoltageProtection
Proper power-supply sequencing is recommended for all CMOS
devices. Do not exceed the absolute maximum ratings, because
stresses beyond the listed ratings may cause permanent damage to
the devices. Always sequence V+ on first, followed by V-, and then
logic inputs. If power-supply sequencing is not possible, add two
small signal diodes or two current limiting resistors in series with
the supply pins for overvoltage protection (Figure 9). Adding
diodes reduces the analog signal range, but low switch resistance
and low leakage characteristics are unaffected.
Maximum Sampling Rate
From the sampling theorem, the sampling frequency needed to
properly recover the original signal should be more than twice
its maximum component frequency. In real applications,
sampling at three or four times the maximum signal frequency is
customary.
The maximum sampling rate of a multiplexer is determined by its
transition time (tTRANS), the number of channels being multiplexed,
and the settling time (tSETTLING) of the sampled signal at the out-
put. The maximum sampling rate is:
_______________
(1)
n (tTRANS + tSETTLING)
Where n = number of channels scanned: 8 for PS398,
4 for PS399. tTRANS is given on the specification table: 150 ns max.
Settling time is the time needed for the output to stabilize within
the desired accuracy band of +1 LSB (least significant bit).
Other factors determining settling time are: signal source imped-
ance, capacitive load at the output. Figure 10 illustrates the steady
state model. To figure out what the settling time due to the multi-
plexer is, we can assume that RS = 0
, and CL = 0. In real life, the
effects of RS and CL should be taken into account when perform-
ing these calculations.
fS =
1
V+
+5V
-5V
COM
GND
V-
N01
N08
A0
A1
A2
EN
f
PS398
=1MHz
Channel
Select
1MHz
Capacitance
Analyzer
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