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參數(shù)資料
| 型號(hào)： | PNP-3050-L22 |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 250 MHz, QCC22 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | PNP-3050-L22 |
Pin Descriptions
PNP-3050-L22
Mnemonic
FUNCTION
RF
RF Output. This pin is AC coupled and should be connected to a non-reflective 50 ohm load.
V1
Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin.
V2
Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin.
REF
Reference Input. This is a CMOS input with a nominal threshold of V2/2 and a dc equivalent
input resistance of 100K ohms. This input can be driven from a CMOS or TTL crystal clock
oscillator or it can be ac coupled.
GND
Digital, Analog and RF Ground.
DA0
Serial Interface. This input functions as CS in MICROWIRE/SPI Bus mode. This input func-
tions as SDA in I
2C BUS mode.
DA1
Serial Interface. This input functions as DATA in MICROWIRE/SPI BUS mode. This input
functions as SCL in I
2C BUS mode.
DA2
Serial Interface. This input functions as CLOCK in MICROWIRE/SPI BUS mode. This input
must be connected to the GROUND in I
2C BUS mode.
LD
Lock Detect. This output is active high and provides a continuous digital lock status.
Absolute Maximum Ratings
V1 to Ground
-0.3 to +5.5 Vdc
V2 to Ground
-0.3 to +3.6 Vdc
REF IN to Ground
-0.3 to (Dvdd + 0.3) Vdc
RF OUT to Ground
+/- 25 Vdc
Digital I/O to Ground
-0.3 to V2 + 0.3 Vdc
Operating Temperature
-40
° to +85°C
Storage Temperature
-55
° to +100°C
Stress above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress
rating only. Operation of the device above the conditions listed
in the operational sections of this specification is not implied.
Ordering Guide
PNP-3050-L22
Model
I
2C Address
Type Code
PNP-3050-L22
Default
P001
PNP-3050A-L22
Default + 1
P001
PNP-3050B-L22
Default + 2
P001
PNP-3050C-L22
Default + 3
P001
CAUTION!
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as
4000V readily accumulate on the human body and test equipment and can dis-
charge without detection. Although the PNP family of synthesizers feature ESD
protection circuitry, permanent damage may occur on devices subjected to high-
energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PNP-3850B-L22-G | PHASE LOCKED LOOP, QCC22 |
| PNP-3850C-L22-G | PHASE LOCKED LOOP, QCC22 |
| PNP-3850A-L22-G | PHASE LOCKED LOOP, QCC22 |
| PNP-3850-L22-G | PHASE LOCKED LOOP, QCC22 |
| PNP-3950B-L22-G | PHASE LOCKED LOOP, QCC22 |
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